TorchLean API

FloatLib.Floats.ExecFloat.Backends.Dispatch.Add.Runtime

Executable addition and subtraction backends #

The generic path handles exact finite arithmetic and the descriptor's exceptional-value policy. The word dispatcher first tries a kernel justified by structural capabilities (native binary32 or binary64, a fixed pair of limbs, the one-word UInt64 kernel for small IEEE formats, or reusable small-word storage for the remaining one-word formats) and returns to that generic path when the specialization declines.

The @[specialize fmt] annotation exposes descriptor-dependent tests to specialization at closed-format call sites. Kernel choice depends only on the descriptor, while operand-dependent acceptance checks stay in the selected kernels. A runtime descriptor is checked on each call.

Refinement theorems live in Add.Proof, so runtime clients can import this module without them.

@[specialize #[0]]

Width-generic compiled addition.

Finite operands use the compact component decoder, and exceptional operands keep the public NaN and infinity policy.

Instances For
    @[specialize #[0]]

    Non-table implementation of addition.

    Structural capabilities select the kernel. Binary32 finite operands use the checked native-word backend. Binary64 first tries the one-word UInt64 kernel of NativeSmallWordAdd, whose capacity contract admits its 53-bit significands, and falls back to its fixed-format chain for wide alignment shifts and boundary results. Eligible two-word layouts use their fixed-limb and width-generic finite chain. Every other IEEE format with at most 30 exponent and 61 fraction bits adds entirely in UInt64 through NativeSmallWordAdd, and the remaining one-word IEEE formats use the shared native-storage decoder before the compiled component kernel. Every decline and every exceptional case falls back to generic.

    Instances For
      @[specialize #[0]]

      Non-table implementation of subtraction.

      Binary32 adds the negated right operand in its checked native backend. Binary64 first tries the one-word UInt64 kernel with the right sign toggled in the storage word, then its fixed-format chain. Eligible two-word layouts use their fixed-limb and width-generic finite subtraction chain. Every other one-word IEEE format with at most 30 exponent and 61 fraction bits subtracts through NativeSmallWordAdd, and the remaining one-word formats use the shared native decoder on the negated operand. Exceptional cases enter exact generic addition with the negated right operand.

      Instances For